 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Freescale Semiconductor Advance Information Document Number: MC10XS3535 Rev. 4.0, 5/2011 Smart Front Corner Light Switch (Triple 10 m and Dual 35 m) The 10XS3535 is designed for low-voltage automotive and industrial lighting applications. Its five low RDS(ON) MOSFETs (three 10 m, two 35 m) can control the high sides of five separate resistive loads (bulbs, Xenon-HID modules and LEDs). Programming, control, and diagnostics are accomplished using a 16-bit SPI interface (3.3 V or 5.0 V). Each output has its own PWM control via the SPI. The 10XS3535 has highly sophisticated failure mode handling to provide high availability of the outputs. Its multiphase control and output edge shaping improves electromagnetic compatibility (EMC) behavior. The 10XS3535 is packaged in a power-enhanced 12 x 12 nonleaded Power QFN package with exposed tabs. Features * Triple 10 m and Dual 35 m high side switches * 16-bit SPI communication interface with daisy chain capability * Current sense output with SPI-programmable multiplex switch and Board Temperature Feedback * Digital diagnosis feature * PWM module with multiphase feature including prescaler * LEDs control including accurate current sensing and low dutycycle capability * Fully-protected switches * Over-current shutdown detection * Power net and reverse polarity protection * Low-power mode * Fail mode functions including autorestart feature * External smart power switch control including current recopy * Lead-free packaging designated by suffix code PNA 12V 5.0V 12V 10XS3535 HIGH SIDE SWITCH Bottom View PNASUFFIX 98ART10511D 24-PIN PQFN PB FREE ORDERING INFORMATION Device MC10XS3535PNA Temperature Range (TA) -40 to 125 C Package 24 PQFN 10XS3535 VCC VBAT CP LIMP OUT1 FLASHER OUT2 IGN RST OUT3 CLOCK OUT4 CS FOG OUT5 S0 FETIN SI SCLK FETOUT CSNS GND Watchdog MCU Smart Switch Figure 1. 10XS3535 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2010-2011. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VCC VBAT CP RUP Vcc failure detection Internal Regulator OV/UV/POR detections Charge Pump CS SO SI SCLK RDWN CLOCK LIMP FOG FLASHER IGN RST Logic LED Control Over-current Detection Open Load Detection Over-temperature Detection OUT1 Gate Drive drain/gate clamp OUT1 RDWN OUT2 OUT2 Over-temperature Prewarning OUT3 OUT3 OUT4 OUT4 OUT5 OUT5 CSNS Selectable Output Current Recopy (Analog MUX) Current Recopy Synchronization VCC Driver for External MOSFET FETIN Temperature Feedback FETOUT GND Figure 2. 10XS3535 Simplified Internal Block Diagram 10XS353 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS FLASHER FETOUT CLOCK SCLK FOG LIMP VCC RST 13 12 11 10 CP GND 16 17 9 8 7 6 5 4 3 IGN 2 SO CS SI 24 14 GND 23 FETIN 1 CSNS GND 22 OUT1 Definition OUT5 18 15 VBAT 19 OUT4 20 OUT3 21 OUT2 Figure 3. 10XS3535 Pin Connections (Transparent Top View Of Package) Table 1. 10XS3535 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on Page 20. Pin Number 1 2 3 4 5 Pin Name FETIN IGN RST FLASHER CLOCK Pin Function Input Input Input Input Input/Output Formal Name External FET Input Ignition Input (Active High) Reset Flasher Input (Active High) Clock Input This pin is the current sense recopy of the external SMART MOSFET. This input wakes the device. It also controls the Outputs 1 and 2 in case of Fail mode activation. This pin has a passive internal pull-down. This input wakes the device. It is also used to initialize the device configuration and fault registers through SPI. This digital pin has a passive internal pull-down. This input wakes the device. This pin has a passive internal pull-down. This pin state depends on RST logic level. As long as RST input pin is set to logic [0], this pin is pulled up in order to report wake event. Otherwise, the PWM frequency and timing are generated from this digital clock input by the PWM module. This pin has a passive internal pull-down. The Fail mode can be activated by this digital input. This pin has a passive internal pull-down. This input wakes the device. This pin has a passive internal pull-down. When this digital signal is high, SPI signals are ignored. Asserting this pin low starts a SPI transaction. The transaction is signaled as completed when this signal returns high. This pin has a passive internal pull-up resistance. This digital input pin is connected to the master microcontroller providing the required bit shift clock for SPI communication. This pin has a passive internal pull-down resistance. 6 7 8 LIMP FOG CS Input Input Input Limp Home Input (Active High) FOG Input (Active high) Chip Select (Active Low) SPI Clock Input 9 SCLK Input 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 10XS3535 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on Page 20. Pin Number 10 11 12 13 Pin Name SI VCC SO FETOUT Pin Function Input Power Output Output Formal Name Master-Out SlaveIn Logic Supply Master-In SlaveOut External FET Gate Definition This data input is sampled on the positive edge of the SCLK. This pin has a passive internal pull-down resistance. SPI Logic power supply. SPI data is sent to the MCU by this pin. This data output changes on the negative edge of SCLK and when CS is high, this pin is high-impedance. This pin controls an external SMART MOSFET by logic level. This output is also called OUT6. If OUT6 is not used in the application, this output pin is set to logic high when the current sense output becomes valid when CSNS sync SPI bit is set to logic [1]. 14,17,23 15 16 22 18 21 20 19 24 GND VBAT CP OUT1 OUT5 OUT2 OUT3 OUT4 CSNS Ground Power Output Output Output Ground Battery Input Charge Pump Output 1 Output 5 Output 2 Output 3 Output 4 Current Sense Output This pin is the ground for the logic and analog circuitry of the device.(1) Power supply pin. This pin is the connection for an external tank capacitor (for internal use only). Protected 35 m high side power output to the load. Protected 10 m high side power output to the load. Output This pin is used to output a current proportional to OUT1:OUT5, FET in current, and it is used externally to generate a ground-referenced voltage for the microcontroller to monitor output current. Moreover, this pin can report a voltage proportional to the temperature on the GND flag. OUT1:OUT5, FET in current sensing and Temperature feedback choice is SPI programmable. Notes 1. The pins 14, 17 and 23 must be shorted on the board. 10XS353 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS Over-voltage Test Range (all OUT[1:5] ON with nominal DC current) Maximum Operating Voltage Load Dump (400 ms) @ 25 C Reverse Polarity Voltage Range (all OUT[1:5] ON with nominal DC current) 2.0 Min @ 25 C VCC Supply Voltage OUT[1:5] Voltage Positive Negative (ground disconnected) Digital Current in Clamping Mode (SI, SCLK, CS, RST, IGN, FLASHER, LIMP and FOG) FETIN Input Current IIN IFETIN VSO VCC VOUT 40 -16 1.0 +10 -1.0 SO, FETOUT, CLOCK and CSNS Outputs Voltage Outputs clamp energy using single pulse method (L = 2 mH; R = 0 ; VBAT = 14 V @150C initial) OUT[1,5] OUT[2:4] ESD Voltage(2) E1,5 E2,3,4 VESD 2000 8000 750 500 30 100 V - 0.3 to VCC + 0.3 V mA mA VBAT - 18 -0.3 to 5.5 V V VBAT 28 40 V V Symbol Value Unit mJ Human Body Model (HBM) Human Body Model (HBM) OUT [1:5], VPWR, and GND Charge Device Model (CDM) Corner Pins (1, 13, 19, 21) All Other Pins (2-12, 14-18, 20, 22-24) THERMAL RATINGS Operating Temperature Ambient Junction Peak Package Reflow Temperature During Reflow(3) Storage Temperature THERMAL RESISTANCE Thermal Resistance, Junction to Case(4) RJC TA TJ TPPRT TSTG C - 40 to 125 - 40 to 150 260 - 55 to 150 C C K/W 1.0 Notes 2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100pF, RZAP = 1500 ) and Charge Device Model. 3. 4. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Typical value guaranteed per design. 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 2 0V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Characteristic POWER INPUTS (VBAT, VCC) Battery Supply Voltage Range Full Performance & Short Circuit Extended Voltage Range(5) Battery Supply Under-voltage (UV flag is set ON) Battery Supply Over-voltage (OV flag is set ON) Battery Voltage Clamp(8) Battery Supply Power on Reset(9) If VBAT < 5.5 V, VBAT = VCC If VBAT < 5.5 V, VCC = 0 VBAT Supply Current @ 25 C and VBAT = 12 V and VCC = 5 V Sleep State Current, Outputs Opened Sleep State Current, Outputs Grounded Normal Mode, IGN = 5 V, RST = 5 V, Outputs Open Digital Supply Voltage Range, Full Performance Digital Supply Undervoltage (VCC Failure) Sleep Current Consumption on VCC @ 25 C and VBAT = 12 V Output OFF Supply Current Consumption on VCC and VBAT = 12 V No SPI 3.0 MHz SPI Communication LOGIC INPUT/OUTPUT (IGN, CS, CSNS, SI, SCLK, CLOCK, SO, FLASHER, RST, LIMP, FOG) Input High Logic Level(6) Input Low Logic Level(6) Voltage Threshold for wake-up (IGN, FLASHER, FOG and RST) Input Clamp Voltage (IGN, FLASHER, LIMP, FOG, CS, SCLK, SI, RST) I = 1.0 mA Input Forward Voltage (IGN, FLASHER, LIMP, FOG, CS, SCLK, SI, RST) I = -1.0 mA Input Passive Pull-up Resistance on CS input(7) Input Passive Pull-down Resistance on SI, SCLK, FLASHER, IGN, FOG, CLOCK, LIMP and RST pins IOH = 1.0 mA SO Low-state Output Voltage IOL = -1.6 mA CLOCK Output Voltage reporting wake-up event (ICLOCK = 1.0 mA) Notes 5. 6. 7. 8. 9. VCLOCKH VSOL - 0.8 0.2 0.95 0.4 - Vcc (7) Symbol Min Typ Max Unit VBAT 7.0 6.0 VBATUV VBATOV VBATCLAMP VBATPOR1 VBATPOR2 IBATSLEEP1 IBATSLEEP2 IBAT VCC VCCUV 5.0 27.5 40 2.0 2.0 - - 5.5 30 - - - 20.0 28.0 6.0 32.5 48 3.0 4.0 V V V V V - - - 3.0 2.2 - 0.5 0.5 10.0 - 2.5 0.2 - - 5.0 5.0 20.0 5.5 2.8 5.0 A A mA V V A mA ICCSLEEP ICC - - 2.6 5.0 VIH VIL VIGNTH VCL_POS 2.0 - 1.0 7.5 - - - - - 200 200 - 0.8 2.2 13 V V V V V VCL_NEG - 2.0 RUP RDWN VSOH 0.8 0.95 - 100 100 -0.3 400 500 k k SO High-state Output Voltage VCC V In extended mode, the functionality is guaranteed but not the electrical parameters. Valid for RST, SI, SCLK, CS, CLOCK, IGN, FLASHER, FOG, and LIMP pins. Valid for the following input voltage range: -0.3 V to VCC + 0.3 V. Outputs shorted to ground, IOUT = + 500 mA and IOUT =OCHI (guaranteed by design). Please refer to Loss of Supply Lines section for more details. 10XS353 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 2 0V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Characteristic LOGIC INPUT/OUTPUT (IGN, CS, CSNS) (CONTINUED) CSNS Tri-state Leakage Current VCC = 5.5 V, CSNS = 5.5 V VCC = 5.0 V, CSNS = 5.5 V VCC = 5.0 V, CSNS = 4.5 V Current Sense Output Clamp Voltage CSNS open and IOUT[1:5] = IFSR OUTPUTS (OUT 1-5) Output Leakage Current in OFF state Sleep mode, Outputs Grounded Normal mode, Outputs Grounded Output Negative Clamp Voltage IOUT = - 500 mA, Outputs OFF Current Sense Output Precision(10) Full-Scale Range (FSR) for LED Control bit = 0 0.75 FSR 0.50 FSR 0.25 FSR 0.10 FSR Full-Scale Range for LED Control bit = 1 (OUT1 and OUT5 only) 0.187 FSR = 0.75 FSRLED 0.125 FSR = 0.50 FSRLED 0.062 FSR = 0.25 FSRLED 0.025 FSR = 0.10 FSRLED Current Sense Output Precision with one calibration point (50% FSR, VBAT = 13.5 at 25 C(12) Current Sense Output Precision with one calibration point (50% FSRLED, VBAT = 13.5 V at 25 C(12) Temperature Drift of Current Sense Output(11) VBAT = 13.5 V, IOUT1,5 = 2.8 A, IOUT2-4 = 5.5 A, reference taken at TA=25 C Minimum Output Current Reported in CSNS for OUT[2-4](14) 10 V VBAT 16 V Minimum Output Current Reported in CSNS for OUT[1,5](14) 10 V VBAT 16 V Minimum Output Current Reported in CSNS for OUT[2-4] in LED Mode(14) I10MIN(CSNS)LED 10 V VBAT 16 V Minimum Output Current Reported in CSNS for OUT[1,5] in LED Mode(14) I35MIN(CSNS)LED 10 V VBAT 16 V Over-temperature Shutdown Thermal Prewarning(13) Output Voltage Threshold TOTS TOTSWARN VOUT_TH I35MIN(CSNS) 65 140 40 155 110 0.475 - - - 175 125 0.5 - mA - mA - 195 140 0.525 C C VBAT I10MIN(CSNS) 250 - - mA mA ICS /T -13 -13 -20 -30 -6.0 -6.0 - - - - - - - 280 13 13 20 30 6.0 6.0 400 % % ppm/C -14 -15 -17 -22 - - - - 14 15 17 22 ICS / ICS VOUT - 22.0 - -16.0 % IOUTLEAK - - 0 20 2.0 25 V A VCSNS 5.0 6.0 7.0 ICSNSLEAK - 5.0 - 10 - 1.0 0 0 0 1.0 1.0 1.0 V A Symbol Min Typ Max Unit Notes 10. 10 V < VBAT < 16 V. ICS / ICS = (measured ICS - targeted ICS)/ targeted ICS with targeted ICS = 5 mA 11. Based on statistical data. Not production tested. ICS /T=[(measured ICS at T1 - measured ICS at T2) / measured ICS at room] / (T1 -T2). 12. 13. 14. Based on statistical analysis covering 99.74% of parts, except 10% of FSR. Please refer to Current Sense section for more details. Parameter guaranteed by design; however, it is not production tested. 10XS3535 Output current value computed after leakage current removal (open load condition) Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 2 0V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Characteristic PARKING LIGHT OUT1 Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 C) VBAT = 13.5 V VBAT = 7.0 V Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V, TA = 150 C) (13) Symbol Min Typ Max Unit RDS(ON)25 - - RDS(ON)150 - RDS(ON)25_LED - - RDS(ON)150_LED - RSD(ON) - IOCHI1 28.0 30.2 29.4 28.3 - 35.0 36.0 35.0 33.8 70 43.5 41.8 40.6 39.3 - 119 - - 70 110 - 59.5 - - 35 55 m m Output Drain-to-Source ON Resistance (IOUT = 1.5 A, TA = 25 C) for LED Control = 1 VBAT = 13.5 V VBAT = 7.0 V Output Drain-to-Source ON Resistance (IOUT = 1.5 A, VBAT = 13.5 V, TA = 150 C) for LED Control = 1 VBAT = -12 V High Over-current Shutdown Threshold 1 VBAT = 16 V, TA = -40 C VBAT = 16 V, TA = 25 C VBAT = 16 V, TA = 125 C (13) m m Reverse Output ON Resistance (IOUT = -2.8 A, TA = 25 C)(15) m A Notes 15. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT. 10XS353 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 2 0V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Characteristic PARKING LIGHT OUT1 (CONTINUED) High Over-current Shutdown Threshold 2 Low Over-current Shutdown Threshold Open Load-current Threshold in ON State(16) Open Load-current Threshold in ON State with LED(17) VOUT = VBAT - 0.8 V Current Sense Full-Scale Range Current Sense Full-Scale Range (18) (18) Symbol Min Typ Max Unit IOCHI2 IOCLO IOL IOLLED 12.3 5.7 0.05 4.0 15.4 7.2 0.2 10.0 5.7 1.6 - 18.5 8.9 0.5 20.0 - - - A A A mA ICS FSR depending on LED Control = 1 ICS FSR_LED RSC1(OUT1) - - 350 A A m Severe short-circuit impedance range(19) LOW BEAM OUT2 Output Drain-to-Source ON Resistance (IOUT = 5.5 A, TA = 25 C) VBAT = 13.5 V VBAT = 7.0 V Output Drain-to-Source ON Resistance (IOUT = 5.5 A, VBAT = 13.5 V, TA = 150 C) VBAT = -12 V High Over-current Shutdown Threshold 1 VBAT = 16 V, TA = -40 C VBAT = 16 V, TA = 25 C VBAT = 16 V, TA = 125 C High Over-current Shutdown Threshold 2 Low Over-current Shutdown Threshold Optional Xenon Bulb Optional H7 Bulb Open Load Current Threshold in ON State(21) Open Load Current Threshold in ON State with LED VOL = VBAT - 0.8 V Current Sense Full-scale Range(23) Optional Xenon Bulb Optional H7 Bulb Severe short-circuit impedance range(19) (22) (19) (20) RDS(ON) - - RDS(ON) - RSD(ON) - IOCHI1 63.2 67.2 66.3 62.5 IOCHI2 IOCLO 17.6 12.1 IOL IOLLED 4.0 ICS FSR - - RSC1(OUT2) 100 21.9 12.5 - - - - 10.0 20.0 0.1 22.0 15.2 0.4 26.4 18.3 1.0 26.2 - 79.0 80.0 79.0 74.5 32.8 20 94.8 92.8 91.7 86.5 39.4 - 17.0 - - 10 15 m m Reverse Source-to-Drain ON Resistance (IOUT = -5.5 A, TA = 25 C) m A A A A mA A m Notes 16. OLLED1, bit D0 in SI data is set to [0]. 17. OLLED1, bit D0 in SI data is set to [1]. 18. For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed. 19. 20. 21. 22. 23. Parameter guaranteed by design; however, it is not production tested. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT. OLLED2, bit D1 in SI data is set to [0]. OLLED2, bit D1 in SI data is set to [1]. For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 2 0V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Characteristic HIGH BEAM OUT3 Output Drain-to-Source ON Resistance (IOUT = 5.5 A, TA = 25 C) VBAT = 13.5 V VBAT = 7.0 V Output Drain-to-Source ON Resistance (IOUT = 5.5 A, VBAT = 13.5 V TA = 150 C)(24) Reverse Source-to-Drain ON Resistance (IOUT = -5.5 A, TA = 25 C)(25) VBAT = -12 V High Over-current Shutdown Threshold 1 VBAT = 16 V, TA = -40 C VBAT = 16 V, TA = 25 C VBAT = 16 V, TA = 125 C High Over-current Shutdown Threshold 2 Low Over-current Shutdown Threshold Open Load Current Threshold in ON State VOL = VBAT - 0.8 V Current Sense Full-scale Range(28) Severe short-circuit impedance range(24) ICS FSR RSC1(OUT3) (26) Symbol Min Typ Max Unit RDS(ON)25 - - RDS(ON)150 - RSD(ON)25 - IOCHI1 65.6 70.1 68.8 65.5 IOCHI2 IOCLO IOL IOLLED 4.0 - 100 10.0 12.7 - 20.0 - - 27.5 12.5 0.1 - 82.0 83.5 82.0 78.0 34.4 15.7 0.4 20 98.4 96.9 95.2 90.5 41.3 18.9 1.0 - 17.0 - - 10 15 m m m A A A A mA Open Load Current Threshold in ON State with LED(27) A m Notes 24. Parameter guaranteed by design; however, it is not production tested. 25. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT. 26. 27. 28. OLLED3, bit D2 in SI data is set to [0]. OLLED3, bit D2 in SI data is set to [1]. For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed. 10XS353 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 2 0V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Characteristic FOG LIGHT OUT4 Output Drain-to-Source ON Resistance (IOUT = 5.5 A, TA = 25 C) VBAT = 13.5V VBAT = 7.0V Output Drain-to-Source ON Resistance (IOUT = 5.5 A, VBAT = 13.5 V, TA = 150 C) (29) (30) Symbol Min Typ Max Unit RDS(ON)25 - - RDS(ON)150 - RSD(ON)25 - IOCHI1 63.2 67.2 66.3 62.5 IOCHI2 IOCLO 26.2 12.1 0.1 4.0 ICS FSR RSC1(OUT4) RDS(ON)25 - - RDS(ON)150 - RDS(ON)25_LED - - RDS(ON)150_LED - RSD(ON)25 - - 70 - 119 - - 70 110 - 59.5 - - 35 55 - 100 - 79.0 80.0 79.0 74.5 32.8 15.2 0.4 10.0 12.5 - 20 94.8 92.8 91.7 86.5 39.4 18.3 1.0 20.0 - - - 17.0 - - 10 15 m m m Reverse Source-to-Drain ON Resistance (IOUT = -5.5 A, TA = 25 C) VBAT = -12 V High Over-current Shutdown Threshold 1 VBAT = 16 V, TA = -40 C VBAT = 16 V, TA = 25 C VBAT = 16 V, TA = 125 C High Over-current Shutdown Threshold 2 Low Over-current Shutdown Threshold Open Load Current Threshold in ON State VOL = VBAT - 0.8 V Current Sense Full-scale Range(33) Severe short-circuit impedance range(29) FLASHER OUT5 Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 C) VBAT = 13.5 V VBAT = 7.0 V (31) A A A A mA IOL IOLLED Open Load Current Threshold in ON State with LED(32) A m m Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V, TA = 150 C)(34) Output Drain-to-Source ON Resistance (IOUT = 1.5 A, TA = 25 C) for LED Control = 1 VBAT = 13.5 V VBAT = 7.0 V Output Drain-to-Source ON Resistance (IOUT = 1.5 A, VBAT = 13.5 V, TA = 150 C) for LED Control = VBAT = -12 V 1(34) m m m Reverse Source-to-Drain ON Resistance (IOUT = -2.8 A, TJ = 25 C)(35) m Notes 29. Parameter guaranteed by design; however, it is not production tested. 30. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT. 31. 32. 33. OLLED4, bit D3 in SI data is set to [0]. OLLED4, bit D3 in SI data is set to [1]. For typical value of ICS FSR, ICSNS = 5.0mA. If the range is exceeded, no current clamp and the precision is no more guaranteed. 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 2 0V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 C under nominal conditions, unless otherwise noted. Characteristic FLASHER OUT5 (CONTINUED) High Over-current Shutdown Threshold 1 VBAT = 16 V, TA = -40 C VBAT = 16 V, TA = 25 C VBAT = 16 V, TA = 125 C High Over-current Shutdown Threshold 2 Low Over-current Shutdown Threshold Open Load Current Threshold in ON State(37) Open Load Current Threshold in ON State with LED VOL = VBAT - 0.8 V Current Sense Full-Scale Range(38) Current Sense Full-Scale Range(18) depending on LED Control = 1 (34) (37) Symbol Min Typ Max Unit IOCHI1 28.0 30.2 29.4 28.3 35.0 36.0 35.0 33.8 15.4 7.2 0.2 10.0 5.7 1.6 - 43.5 41.8 40.6 39.3 18.5 8.9 0.5 20.0 - - - A IOCHI2 IOCLO IOL IOLLED 12.3 5.7 0.05 4.0 A A A mA ICS FSR ICS FSR_LED RSC1(OUT5) VH MAX VH MIN IFET IN VCLIN - - 350 A A m Severe short-circuit impedance range SPARE FETOUT / FETIN FETOUT Output High Level @ I = 1.0 mA FETOUT Output Low Level @ I = -1.0 mA FETIN Input Full Scale Range Current FETIN Input Clamp Voltage IFET IN = 5mA, CSNS open Drop Voltage between FETIN and CSNS for MUX[2:0]=110 IFET IN = 5 mA, 5.5 V > CSNS > 0.0 V FETIN Leakage Current when external current switch sense is enabled VCC > VFET IN > 0 V, 5.5 V > VCC 4.5 V, CSNS open VCC > VFET IN > 0 V, 4.5 V > VCC > 0, CSNS open TEMPERATURE OF GND FLAG Analog Temperature Feedback Range Analog Temperature Feedback at TA = 25 C with 5.0 k > RCSNS > 500 Analog Temperature Feedback Derating with 5.0 k > RCSNS > 500 Analog Temperature Feedback Precision(34) Analog Temperature Feedback Precision with calibration point at 25 C (34) (34) 0.8 - - 5.3 - 0.2 5.0 - - - - - 0.4 - 13 VCC V mA V V VDRIN 0.0 IFETINLEAK - 1.0 - 1.0 5.0 1.0 0.4 A TFEED_RANGE VT_FEED VDT_FEED VDT_ACC VDT_ACC_CAL -40 920 10.9 -15 -5.0 1025 11.3 - - 150 1140 11.7 15 5.0 C mV mV/C C C Notes 34. Parameter guaranteed by design; however, it is not production tested. 35. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VBAT. 36. 37. 38. OLLED5, bit D4 in SI data is set to [0]. OLLED5, bit D4 in SI data is set to [1]. For typical value of ICS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed. 10XS353 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 3.0V VCC 5.5V, 7.0V VBAT 20V, - 40C TA 125C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic POWER OUTPUTS TIMING (OUT1 TO OUT5) Current Sense Valid Time on resistive load only(39) SR bit = 0 SR bit = 1 Current Sense Synchronization Time on FETOUT SR bit = 0 SR bit = 1 Current Sense Settling Time on resistive load only SR bit = 0 IOUT = 2.8 A for OUT1 and OUT5 IOUT = 5.5 A for OUT2, OUT3, and OUT4 SR bit = 1 IOUT =0.7 A for OUT1 and OUT5 IOUT = 1.4 A for OUT2, OUT3, and OUT4 Driver Output Negative Slew Rate (70% to 30% @ VBAT = 14 V) SR bit = 0 IOUT = 2.8 A for OUT1 and OUT5 IOUT = 5.5 A for OUT2, OUT3, and OUT4 SR bit = 1 IOUT = 0.7 A for OUT1 and OUT5 IOUT = 1.4 A for OUT2, OUT3, and OUT4 Driver Output Matching Slew Rate (SRR /SRF) (70% to 30% @ VBAT = 14 V @ 25 C) SR bit = 0: IOUT = 2.8 A for OUT1 and OUT5 and IOUT = 5.5 A for OUT2/3/4 SR bit = 1: IOUT = 0.7 A for OUT1 and OUT5 and IOUT = 1.4 A for OUT2/3/4 Driver Output Turn-ON Delay (SPI ON Command [No PWM, CS Positive Edge] to Output = 50% VBAT @ VBAT = 14 V) (see Figure 6) SR bit = 0: IOUT = 2.8 A for OUT1 and OUT5 and IOUT = 5.5 A for OUT2/3/4 SR bit = 1: IOUT = 0.7 A for OUT1 and OUT5 and IOUT = 1.4 A for OUT2/3/4 Driver Output Turn-OFF Delay (SPI OFF command [CS Positive Edge] to Output = 50% VBAT @ VBAT = 14 V) (see Figure 6) SR bit = 0: IOUT = 2.8 A for OUT1 and OUT5 and IOUT = 5.5 A for OUT2/3/4 SR bit = 1: IOUT = 0.7 A for OUT1 and OUT5 and IOUT = 1.4 A for OUT2/3/4 Notes 39. Not production tested. SR 0.8 0.8 1.0 1.0 1.2 1.2 s 50 25 - - 120 65 s 50 25 - - 120 65 0.20 0.30 0.40 0.55 0.80 1.05 0.10 0.14 0.25 0.30 0.56 0.56 SRF 0.20 0.30 0.40 0.55 0.80 1.05 V/s 0.10 0.14 0.25 0.30 0.56 0.56 (39) Symbol Min Typ Max Unit t CSNS(VAL) - - 90 45 130 70 10 150 75 s t CSNS(SYNC) - - 185 110 30 s t CSNS(SET) SRR - s V/s Driver Output Positive Slew Rate (30% to 70% @ VBAT = 14 V) t DLYON t DLYOFF 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 3.0V VCC 5.5V, 7.0V VBAT 20V, - 40C TA 125C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic POWER OUTPUTS TIMING (OUT1 TO OUT5) (CONTINUED) Driver Output Matching Time (t DLY(ON) - t DLY(OFF)) @ Output = 50% VBAT with VBAT = 14 V, f PWM = 240 Hz, PWM = 50%, @ 25 C SR bit = 0: IOUT = 2.8 A for OUT1 and OUT5 and IOUT = 5.5 A for OUT2/3/4 SR bit = 1: IOUT = 0.7 A for OUT1 and OUT5 and IOUT = 1.4 A for OUT2/3/4 PWM MODULE Nominal PWM Frequency Range(40) Clock Input Frequency Range Output PWM Duty Cycle maximum range for 11 V < VBAT < 18 V(40), (41) Output PWM Duty Cycle linear range for 11 V < VBAT < 18 V(42) Output PWM Duty Cycle range for full diagnostic for 11 V < VBAT < 18 V(43) 200 Hz Output PWM frequency 400 Hz Output PWM frequency f PWM f CLK PWM_MAX PWM_LIN PWM_DIAG Symbol Min Typ Max Unit t RF - 30 - 15 - - 30 15 s 30.0 7.68 4.0 5.5 - - - - 400 51.2 96 96 Hz kHz % % % 5.5 11 - - 96 90 Notes 40. Not production tested. 41. The PWM ratio is measured at VOUT = 50% of VBAT in nominal range of PWM frequency. It is possible to put the device fully on (PWM duty cycle = 100%) and fully off (PWM duty cycle = 0%). Between 4%-96%, OCHI1,2, OCLO and open load are available in ON state. See Figure 6, Output Slew Rate and Time Delays. 42. Linear range is defined by output duty cycle to SPI duty cycle configuration +/-1 LSB. For values outside linear duty cycle range, a calibration curve is available. 43. Full diagnostic corresponds to the availability of the following features: output current sensing, output status and open load detection. Not production tested. 10XS353 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 3.0V VCC 5.5V, 7.0V VBAT 20V, - 40C TA 125C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic WATCHDOG TIMING Watchdog Timeout (SPI Failure) I/O PLAUSIBILITY CHECK TIMING Fault Shutdown Delay Time (from Overtemperature or OCHI1 or OCHI2 or OCLO or UV Fault Detection to Output = 50% VBAT without round shaping t WDTO 50 75 100 ms Symbol Min Typ Max Unit t SD - 7.0 30 s feature for turn off) Under-voltage Deglitch Time(44) High Over-current Threshold Time 1 for OUT1 and OUT5 for OUT2, OUT3, and OUT4 High Over-current Threshold Time 2 for OUT1 and OUT5 for OUT2, OUT3, and OUT4 Autorestart Period for OUT1 and OUT5 for OUT2, OUT3, and OUT4 Autorestart Over-current Shutdown Delay Time for OUT1 and OUT5 for OUT2, OUT3, and OUT4 Limp Home Input pin Deglicher Time Cyclic Open Load Detection Timing with Flasher Toggle Timeout Fog Toggle Timeout Ignition Toggle Timeout Clock Input Low Frequency Detection Range Clock Input High Frequency Detection Range LED(45) t LIMP t OCHI_AUTO 3.5 7.0 7.0 105 1.4 1.4 1.4 1.0 100 5.0 10.0 10.0 150 2.3 2.3 2.3 2.0 200 6.5 13.0 13.0 195 3.0 3.0 3.0 4.0 400 ms ms s s s kHz kHz t UV t1 1.5 2.5 5.0 s ms 7.0 14 10 20 75 150 75 150 13.5 26 ms 97.5 195 ms 97.5 195 ms t2 52.5 105 tAUTORST 52.5 105 t OLLED t FLASHER t FOG t IGNITION f LCLK DET f HCLK DET Notes 44. This time is measured from the VBAT(UV) level to the fault reporting. Parameter guaranteed in testmode. 45. IOLLEDn bit (where "n" corresponds to respective outputs 1 through 5) in SI data is set to logic [1]. Refer to Table 7, Serial Input Address and Configuration Bit Map, page 26. 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 15 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 3.0V VCC 5.5V, 7.0V VBAT 20V, - 40C TA 125C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic SPI INTERFACE CHARACTERISTICS Maximum Frequency of SPI Operation Rising Edge of CS to Falling Edge of CS (Required Setup Time)(46) (46) Symbol Min Typ Max Unit f SPI t CS t LEAD t WSCLKH t WSCLKL (46) - - - - - - - - - - - - - 50 25 25 3.0 1.0 500 167 167 167 83 83 MHz us ns ns ns ns ns ns ns Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) Required High State Duration of SCLK (Required Setup Time) Required Low State Duration of SCLK (Required Setup (46) Time)(46) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) SI to Falling Edge of SCLK (Required Setup Time) Falling Edge of SCLK to SI (Required Setup SO Rise Time CL = 80 pF SO Fall Time CL = 80 pF SI, CS, SCLK, Incoming Signal Rise Time(47) (47) (47) t LAG t SI(SU t SI HOLD t RSO Time)(47) - 25 50 ns t FSO - 25 - - - 65 50 50 50 145 145 t RSI t FSI t SO(EN) t SO(DIS) - - - - ns ns ns ns SI, CS, SCLK, Incoming Signal Fall Time Time from Falling Edge of SCLK to SO Time from Rising Edge of SCLK to SO Notes 46. 47. 48. 49. Low-impedance(48) High-impedance(49) Maximum setup time required for the 10XS3535 is the minimum guaranteed time needed from the microcontroller. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0 k on pull-up on CS. Time required for output status data to be terminated at SO. 1.0 k on pull-up on CS. 10XS353 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS TwRSTB t ENBL VIL VIL t CS TCSB TENBL 90% VCC 0.7VDD CS CSB 10% VCC 0.7VDD tTlead LEAD t WSCLKH TwSCLKh t RSI TrSI VIH V IH VIL V IL SCLK SCLK 90% VCC 0.7VDD 10% VCC 0.2VDD t LAG Tlag VIH VIH VIL V t TSIsu SI(SU) t WSCLKL TwSCLKl t SI(HOLD) TSI(hold) IL tTfSI FSI VIH V Valid Don't Care IH SI SI Don't Care 90% VCC 0.7 VDD 0.2VDD CC 10% V Valid Don't Care VIL VIL Figure 4. Input Timing Switching Characteristics t RSI t FSI TrSI 2.0 3.5V V TfSI VOH VOH 50% 1.0V 0.8 V VOL VOL SCLK SCLK t SO(EN) TdlyLH SO SO 90% VCC 0.7 VDD VOH VOH VOL VOL 0.2 VDD CC 10% V TrSO t RSO TVALID tVALID Low-to-High Low to High SO SO 90% V High to Low High-to-Low 0.7 VDD CC TfSO t FSO VOH VOH TdlyHL tSO(DIS) 0.2VDD 10% VCC VOL VOL Figure 5. SCLK Waveform and Valid SO Data Delay Time 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 17 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS CS High logic level Low logic level VOUT[1:5] VPWR RPWM 50%VPWR Time Time VOUT[1:5] 70% VPWR 30% VPWR t DLY(ON) t DLY(OFF) SR F Time SR R Figure 6. Output Slew Rate and Time Delays CS High logic level Low logic level IOUT[1:5] IMAX Time Time t DLY(ON) ICSNS t CSNS(SET) t DLY(OFF) t CSNS(VAL) Time VFETOUT High logic level Low logic level Figure 7. Current Sensing Time Delays t CSNS(SYNC) with CSNS sync bit = 1 Time 10XS353 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 10XS3535 is designed for low-voltage automotive and industrial lighting applications. Its five low RDS(ON) MOSFETs (three 10 m and two 35 m) can control the high sides of five separate resistive loads (bulbs). Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. FUNCTIONAL PIN DESCRIPTION SUPPLY VOLTAGE (VBAT) The VBAT pin of the 10XS3535 is the power supply of the device. In addition to its supply function, this tab contributes to the thermal behavior of the device by conducting the heat from the switching MOSFETs to the printed circuit board. Ch.1 Ch.2 Ch.3 Ch.4 SUPPLY VOLTAGE (VCC) This is an external voltage input pin used to supply the digital portion of the circuit and the gate driver of the external SMART MOSFET. Total 0 90 180 270 0 GROUND (GND) This pin is the ground of the device. CLOCK INPUT / WAKE-UP OUTPUT (CLOCK) When the part is in Normal Mode (RST=1), the PWM frequency and timing are generated from the rising edge of clock input by the PWM module. The clock input frequency is the selectable factor 27 = 128 or 28 = 256 of the PWM frequency per output, depending PR bit value. The OUT1:6 can be controlled in the range of 4% to 96% with a resolution of 7 bits of duty cycle (bits D[6:0]). The following table describes the PWM resolution. On/Off (Bit D7) 0 1 1 1 1 Duty cycle (7 bits resolution) X 0000000 0000001 0000010 1111111 Output state OFF PWM (1/128 duty cycle) PWM (2/128 duty cycle) PWM (3/128 duty cycle) fully ON Ch.1 Ch.2 Ch.3 Ch.4 Total 0 90 180 270 0 The synchronization of the switching phases between different IC is provided by an SPI command in combination with the CS input. The bit in the SPI is called PWM sync (initialization register). In Normal mode, no PWM feature (100% duty cycle) is provided in the following instances: *with the following SPI configuration: D7:D0=FF. *In case of clock input signal failure (out of f PWM), the outputs state depends of D7 bit value (D7=1=ON) in Normal mode. In Fail mode, the ouputs state depend on IGN, FLASHER, and FOG pins. If RST=0, this pin reports the wake-up event for wake=1 when VBAT and VCC are in operational voltage range. The timing includes four programmable PWM switching phases (0, 90, 180, and 270) to improve overall EMC behavior of the light module. The amplitude of the input current is divided by four while the frequency is 4 times the original one. The two following pictures illustrate this behavior. LIMP HOME INPUT (LIMP) The Fail mode of the component can be activated by this digital input port. The signal is "high active", meaning the Fail mode can be activated by a logic high signal at the input. 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION IGNITION INPUT (IGN) The ignition input wakes the device. It also controls the Fail mode activation. The signal is "high active", meaning the component is active in case of a logic high at the input. FET OUT OUTPUT (FETOUT) This output pin is used to control an external MOSFET (OUT6). The high level of the FETOUT Output is VCC, if VBAT and VCC are available, in case FETOUT is a controlled ON. FETOUT is not protected if there is a short-circuit or undervoltage on VBAT. In case of a reverse battery, OUT6 is OFF. FLASHER INPUT (FLASHER) The flasher input wakes the device. It also controls the Fail Mode activation. The signal is "high active", meaning the component is active in case of a logic high at the input. FOG INPUT (FOG) The fog input wakes the device. It also controls the Fail Mode activation. The signal is "high active", meaning the component is active in case of a logic high at the input. FET IN INPUT (FETIN) This input pin gives the current recopy of the external MOSFET. It can be routed on CSNS output by a SPI command. RESET INPUT (RST) This input wakes the device when the RST pin is at logic [1]. It is also used to initialize the device configuration and the SPI faults registers when the signal is low. All SI/SO registers described Table 7 and Table 10 are reset. The fault management is not affected by RST. SPI PROTOCOL DESCRIPTION The SPI interface has a full-duplex, three-wire, synchronous data transfer with four I/O lines associated with it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip Select (CS). The SI/SO pins of the 10XS3535 device follow a first-in, first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 3.3 V and 5.0 V CMOS logic levels, supplied by VCC. The SPI lines perform the following functions: CURRENT SENSE OUTPUT (CSNS) The current sense output pin is an analog current output or a voltage proportional to the temperature on the GND flag. The routing to the external resistor is SPI programmable. This current sense monitoring may be synchronized in case of the OUT6 is not used. So, the current sense monitoring can be synchronized with a rising edge on the FETOUT pin (tCSNS(SYNC)) if CSNS sync SPI bit is set to logic [1]. Connection of the FETOUT-pin to a MCU input pin allows the MCU to sample the CSNS-pin during a valid time-slot. Since this falling edge is generated at the end of this timeslot, upon a switch-off command, this feature may be used to implement maximum current control. SERIAL CLOCK (SCLK) The SCLK pin clocks the internal shift registers of the 10XS3535 device. The SI pin accepts data into the input shift register on the falling edge of the SCLK signal, while the SO pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important that the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has a passive pull-down, RDWN. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tristated (high-impedance) (see Figure 8). CHARGE PUMP (CP) An external capacitor is connected between this pin and the VBAT pin. It is used as a tank for the internal charge pump. Its value is 100 nF 20%, 25 V maximum. 10XS353 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CSB CS CS SCLK SI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SO OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 NOTES: 1. 2. 3. Notes RSTB is in a logic H state during the above operation. 1. D15 : D15 relate to the most recent ordered entry of entry of data into device. the device. DO, D1, D2, ... , and D0 relate to the most recent ordered program data into the LUX IC device. OD0, OD1,2. OD15 : OD0 relate to the first 16 16 bits of ordered fault and statusthe LUX IC of the device. OD2, ..., and OD15 relate to the first bits of ordered fault and status data out of data out Figure 8. Single 16-Bit Word SPI Communication SERIAL INPUT (SI) The SI pin is a serial interface command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, starting with D15 to D0. SI has a passive pull-down, RDOWN. CHIP SELECT (CS) The CS pin enables communication with the master device. When this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the master device. The 10XS3535 device latches in data from the Input Shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the Shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has a passive pull-up, RUP. SERIAL OUTPUT (SO) The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES SLEEP MODE The Sleep mode is the default mode of the 10XS3535. This is the state of the device after first applying battery voltage (VBAT) and prior to any I/O transitions. This is also the state of the device when IGN, FOG, FLASHER, and RST are logic [0] (wake=0). In the Sleep mode, the outputs and all internal circuitry are OFF to minimize current draw. In addition, all SPI-configurable features of the device are reset. The 10XS3535 will transit to two modes (Normal and Fail) depending on wake and fail signals (see Fig13). The transition to the other modes is according following signals: * Wake = IGN or IGN_ON or FLASHER or FLASHER_ON or RST or FOG or FOG_ON * Fail = VCC fail or SPI fail or External limp D7 bit D0-D6 bits Output Over-current FAIL MODE The 10XS3535 is in Fail mode when: * Wake = 1 * Fail = 1 NORMAL MODE The 10XS3535 is in Normal mode when: * Wake = 1 * Fail = 0 In Normal operating mode the power outputs are under full control of the SPI as follows: * The outputs 1 to 6, including multiphase timing and selectable slew-rate, are controlled by the programmable PWM module. * The outputs 1 to 5 are switched OFF in case of an under-voltage on VBAT. * The outputs 1 to 5 are protected by the selectable overcurrent double window and over-temperature shutdown circuit. * The digital diagnosis feature transfers status of the smart outputs via SPI. * The analog current sense output (current recopy feature) can be routed by SPI. * The outputs 1 and 5 can be configured to control LED loads: RDS(ON) is increased by a factor of 2 and the current recopy ratio is scaled by a factor of 4. * The SPI reports NM=1 in this mode. The figure below describes the PWM, outputs and overcurrent behavior in Normal mode. In Fail mode: * The outputs are under control of external pins (see Table 5) * The outputs are fully protected in case of an overload, over-temperature and under-voltage (on VBAT or on VCC). * The SPI reports continuously the content of address 11, disregard to previous requested output data word. * Analog current sense is not available. * Output 2 is configured in Xenon mode. * In case of an overload (OCHI2 or OCLO) conditions or under-voltage on VBAT, the outputs are under control of autorestart feature. * In case of serious overload condition (OCHI1 or OT) the corresponding output is latched OFF until a new wakeup event (wake=0 then 1). IGN_ON IGN (external) OUT[1,2] Over-current 1.4 sec min Table 5. Limp Home Output State Output 1 Parking Light IGN Pin Output 2 Low Beam IGN Pin Output 3 High Beam OFF Output 4 Fog Light FOG Pin Output 5 Flasher FLASHER Pin External Switch Spare OFF 10XS353 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES AUTORESTART STRATEGY The autorestart circuitry is used to supervise the outputs and reactivate high side switches in cases of overload or under-voltage failure conditions, to provide a high availability of the outputs. Autorestart feature is available in Fail mode when no supervising intelligence of the microcontroller is available. Autorestart is activated in case of overload condition (OCHI2 or OCLO) or under-voltage condition on VBAT (see Figure 12). The autorestart switches ON the outputs. During ON state of the switch OCHI1 window is enabled for tochi_Auto, then after the output is protected by OCLO. In case of under-voltage in Fail mode, the outputs 1 to 5 will be latched off. The corresponding output is switched on only after its autorestart period (tAUTORST-T1 or tAUTORST-T2). The Autorestart is not limited in time. TRANSITION FAIL TO NORMAL MODE To leave the Fail mode, the fail condition must be removed (fail=0). The microcontroller has to toggle the SPI D10 bit (0 to 1) to reset the watchdog bit; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode. TRANSITION NORMAL TO FAIL MODE To leave the Normal mode, a fail condition must occur (fail=1). The previous latched faults are reset by the transition into Fail mode. If the SI is shorted to VCC, the device transmits to Fail Safe mode until the WD bit toggles through the SPI (from [0] to [1]). All settings are according to predefined values (all bits set to logic [0]). Output current OCHI1 OCLO or UV fault START-UP SEQUENCE The 10XS3535 enters in Normal mode after start-up if following sequence is provided: *VBAT and VCC power supplies must be above their under-voltage thresholds (Sleep mode). OCLO tochi_auto Auto period time *generate wake up event (wake=1) from 0 to 1 on RST. The device switches to Normal mode. *apply PWM clock after maximum 200 s (min. 50 s). *send SPI command to the Device status register to clear the clock fail flag to enable the PWM module to start. Figure 10 describes the wake-up block diagram. Figure 9. Over-current window in case of Autorestart In case of OCHI1 or OT, the switch is latched OFF until wake-up (wake=0 then 1). In case of OCLO or under-voltage, the output switch OFF and after auto restart period (150 ms for 10 mohm or 75 ms for 35 mOhm) turn ON again. 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES POWER OFF MODE The 10XS3535 is in Power OFF mode when the battery voltage is below VBATPOR[1,2] thresholds. For more details, please refer to Loss of VBAT paragraph. (wake=0) (wake=1) and (fail=1) * Sleep (fail=0) and (wake=1) (wake=0) VBAT > VBATPOR[1,2] VBAT < VBATPOR[1,2] VBAT < VBATPOR[1,2] VBAT < VBATPOR[1,2] Power OFF Normal Fail (fail=0) and (wake=1) (fail=1) and (wake=1) Notes: * only available in case of Vcc fail condition wake = (RST = 1) OR (IGN_ON = 1) OR (Flasher_ON = 1) OR (FOG_ON = 1) fail = (VCC_fail = 1) OR (SPI_fail = 1) OR (ext_limp = 1) Figure 10. Operating Modes State Machine 10XS353 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES VBAT wake Wake-up bar VBAT IGN Deglitcher IGN_ON VCC Internal regulator Dig2.5V FLASHER Flasher_ON Deglitcher Oscillator FOG Fog_ON Deglitcher Fault management PWM freq detector SPI registers RST VCC fail SPI fail External Limp PWM module OR Fail reset VCC OR UVF CLOCK 1.4 sec min external external_ON external: IGN, FLASHER, FOG external_ON: IGN_ON, FLASHER_ON, FOG_ON Figure 11. Wake-up block diagram 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS SERIAL INPUT COMMUNICATION SPI communication compliant to 3.3 V and 5.0 V is accomplished using 16-bit messages. A message is transmitted by the master starting with the MSB, D15, and ending with the LSB, D0. Each incoming command message on the SI pin can be interpreted using the bit assignment described in Table 6. The 5 bits D15 : D11, called register address bits, are used to select the command register. Bit D10 is the watchdog bit. The remaining 10 bits, D9 : D0, are used to configure and control the output and its protection features. Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable or to confirm transmitted data as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. All SPI registers are reset (all bit equal 0) in case of RST equal 0 or fail mode (Fail=1). Table 6. SI Message Bit Assignment Bit Sig MSB SI Msg Bit D15 : D11 D10 LSB D9 : D0 Message Bit Description Register address bits. Watchdog in: toggled to satisfy watchdog requirements. Used to configure inputs, outputs, device protection features, and SO status content. DEVICE REGISTER ADDRESSING The register addresses (D15 : D11) and the impact of the serial input registers on device operation are described in this section. Table 7 summarizes the SI registers. Table 7. Serial Input Address and Configuration Bit Map SI Address SI Register D1 D1 D1 D1 D1 D10 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 WD WD WD WD WD D9 0 LEDControl5 SI Data D8 0 0 PR1 SR1 0 Phase1 Phase1 Phase1 Phase1 Phase1 D7 FOGen 0 PR2 SR2 0 ONoff ONoff ONoff ONoff ONoff D6 PWM sync 0 PR3 SR3 0 PWM6 PWM6 PWM6 PWM6 PWM6 D5 Xenon LEDControl1 D4 MUX2 D3 MUX1 D2 MUX0 D1 SOA1 D0 SOA0 Initialization Config OL Config Prescaler Config SR OLLED5 OLLED4 OLLED3 OLLED2 OLLED1 0 0 0 0 PR4 SR4 PR5 SR5 PR6 0 0 1 CSNS sync 0 0 0 PWM5 PWM5 PWM5 PWM5 PWM5 Config CSNS 0 Control OUT1 Control OUT2 Control OUT3 Control OUT4 Control OUT5 Control External Switch RESET 0 0 0 0 0 NO_OCHI5 NO_OCHI4 NO_OCHI3 NO_OCHI2 NO_OCHI1 WD Phase2 WD Phase2 WD Phase2 WD Phase2 WD Phase2 PWM4 PWM4 PWM4 PWM4 PWM4 PWM3 PWM3 PWM3 PWM3 PWM3 PWM2 PWM2 PWM2 PWM2 PWM2 PWM1 PWM1 PWM1 PWM1 PWM1 PWM0 PWM0 PWM0 PWM0 PWM0 0 X 1 X 1 X 1 X 0 X WD Phase2 0 0 Phase1 0 ONoff 0 PWM6 0 PWM5 0 PWM4 0 PWM3 0 PWM2 0 PWM1 0 PWM0 0 Note: testmode address used only by FSL is D[15:11]=01111 with RST pin voltage higher than 8V typ. X = Don't care and 0 = need to rewrite logic "0" 10XS353 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS ADDRESS 00000 -- INITIALIZATION The Initialization register is used to read the various statuses, choose one of the six outputs current recopy, load the H7 bulbs profile for OUT2 only, enable the FOG pin and synchronize the switching phases between different devices. The register bits D1 and D0 determine the content of the 16 bits of the next SO data. (Refer to the section entitled Serial Output Communication (Device Status Return Data) beginning on page 28.) Table 8 describes the register of initialization. The watchdog timeout is specified by t WDTO parameter. As long as the WD bit (D10) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), the device will operate normally. If an internal watchdog timeout occurs before the WD bit is toggled, the device will revert to Fail mode. All registers are cleared. To exit the Fail mode, send valid SPI communication with WD bit = 1. Table 8. Initialization Register SI Address D15 0 D14 0 D13 0 D12 0 D11 0 D10 WD D9 0 D8 0 D7 FOGen D6 PWM sync SI Data D5 Xenon D4 MUX2 D3 MUX1 D2 MUX0 D1 SOA1 D0 SOA0 D6 (PWM sync) = 0, No synchronization D6 (PWM sync) = 1, Synchronization on CSB positive edge D5 (Xenon) = 0, Xenon D5 (Xenon) = 1, H7 Bulb D7 (FOGen) = 0, FOG pin does not control the output 4 D7 (FOGen) = 1, FOG input controls the output 4 D4, D3, D2 (MUX2, MUX1, MUX0) = 000, No current sense D4, D3, D2 (MUX2, MUX1, MUX0) = 001, OUT1 current sense D4, D3, D2 (MUX2, MUX1, MUX0) = 010, OUT2 current sense D4, D3, D2 (MUX2, MUX1, MUX0) = 011, OUT3 current sense D4, D3, D2 (MUX2, MUX1, MUX0) = 100, OUT4 current sense D4, D3, D2 (MUX2, MUX1, MUX0) = 101, OUT5 current sense D4, D3, D2 (MUX2, MUX1, MUX0) = 110, External Switch current sense D4, D3, D2 (MUX2, MUX1, MUX0) = 111, Temperature analog feedback ADDRESS 00001 -- CONFIGURATION OL The Configuration OL register is used to enable the open load detection for LEDs in Normal Mode (OLLEDn in Table 7, page 26) and to active the LED Control. When bit D0 is set to logic [1], the open load detection circuit for LED is activated for output 1. When bit D0 is set to logic [0], open load detection circuit for standard bulbs is activated for output 1. When bit D5 is set to logic [1], the LED Control is activated for output 1. ADDRESS 00011 -- CONFIGURATION CSNS The Configuration Current Sense register is used to disable the high over-current shutdown phase (OCHI1 and OCHI2 dynamic levels) in order to activate immediately the current sense analog feedback. When bit D9 is set to logic [1], the current sense synchronization signal is reported on FETOUT output pin. When the corresponding NO_OCHI bit is set to logic [1], the output is only protected with OCLO level. And the current sense is immediately available if it is selected through SPI, as described in Figures 13. The NO_OCHI bit per output is automatically reset at each corresponding ONoff bit transition from logic [1] to [0] and in case of over-temperature or overcurrent fault. All NO_OCHI bits are also reset in case of under-voltage fault detection. ADDRESS 00010 -- CONFIGURATION PRESCALER AND SR Two configuration registers are available at this address. The Configuration Prescaler when D9 bit is set to logic [0] and Configuration SR when D9 bit is set to logic [1]. The Configuration Prescaler register is used to enable the PWM clock prescaler per output. When the corresponding PR bit is set to logic [1], the clock prescaler (reference clock divided by 2) is activated for the dedicated output. The SR Prescaler register is used to increase the output slew-rate by a factor of 2. When the corresponding SR bit is set to logic [1], the output switching time is divided by 2 for the dedicated output. ADDRESS 01001 -- CONTROL OUT1 Bits D9 and D8 control the switching phases as shown in Table 9. Table 9. Switching Phases D9 : D8 00 01 PWM Phase 0 90 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 9. Switching Phases 10 11 180 270 new message data is clocked into the SI pin. The first 16 bits of data clocking out of the SO, and following a CS transition, is dependant upon the previously written SPI word (SOA1 and SOA0 defined in the last SPI initialization word). Any bits clocked out of the SO pin after the first 16 will be representative of the initial message bits clocked into the SI pin since the CS pin first transitioned to a logic [0]. This feature is useful for daisy chaining devices. A valid message length is determined following a CS transition of logic [0] to logic [1]. If the message length is valid, the data is latched into the appropriate registers. A valid message length is a multiple of 16 bits. At this time, the SO pin is tri-stated and the fault status register is now able to accept new fault status information. The output status register correctly reflects the status of the Initialization-selected register data at the time that the CS is pulled to a logic [0] during SPI communication and / or for the period of time since the last valid SPI communication, with the following exceptions: *The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred. *Battery transients below 6.0 V, resulting in an undervoltage shutdown of the outputs, may result in incorrect data loaded into the SPI register, except the UVF fault reporting (OD13). Bit D7 at logic [1] turns ON OUT1. OUT1 is turned OFF with bit D7 at logic [0]. This register allows the master to control the duty cycle and the switching phases of OUT1. The duty cycle resolution is given by bits D6 : D0. D7 = 0, D6 : D0 = XX output OFF. D7 = 1, D6 : D0 = 00 output ON during 1/128. D7 = 1, D6 : D0 = 1A output ON during 27/128 on PWM period. D7 = 1, D6 : D0 = 7F output continuous ON (no PWM). ADDRESS 01010 -- CONTROL OUT2 Same description as OUT1. ADDRESS 01011 -- CONTROL OUT3 Same description as OUT1. ADDRESS 01100 -- CONTROL OUT4 Same description as OUT1. ADDRESS 01101 -- CONTROL OUT5 Same description as OUT1. SERIAL OUTPUT BIT ASSIGNMENT The contents of bits OD15 : OD0 depend on bits D1: D0 from the most recent initialization command SOA[1:0] (refer to Table 7, page 26), as explained in the paragraphs that follow. The register bits are reset by a read operation and also if the fault is removed. Table 10 summarizes the SO register content. Bit OD10 reflects Normal mode (NM). ADDRESS 01110 -- CONTROL EXTERNAL SWITCH Same description as OUT1. ADDRESS 01111 -- TEST MODE This register is reserved for test and is not available with SPI during normal operation. SERIAL OUTPUT COMMUNICATION (DEVICE STATUS RETURN DATA) When the CS pin is pulled low, the output register is loaded. Meanwhile, the data is clocked out MSB first as the 10XS353 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 10. Serial Output Bit Map Description Previous Status / SI Data Mode SO SO A1 Fault Status Overload Status Device Status Output Status Reset 0 0 1 A0 0 1 0 SO Data OD15 OD14 OD13 OD12 OD11 OD10 OD9 0 0 1 0 1 0 UVF UVF UVF OTW OTW OTW OTS OTS OTS NM NM NM OL5 OC5 0 OD8 OVL5 OTS5 OV OD7 OL4 OD6 OD5 OD4 OD3 OL2 OC2 OD2 OVL2 OTS2 OD1 OL1 OD0 OVL1 OVL4 OL3 OVL3 OC4 OTS4 OC3 OTS3 FOG_ FLAS IGN_ ON HER_ ON ON X 0 X 0 X 0 RC OC1 OTS1 FOG FLASHER IGN CLOCK pin pin pin fail OUT4 OUT3 OUT2 OUT1 1 X 1 X 1 0 1 0 UVF 0 OTW 0 OTS 0 NM 1 0 0 0 0 OUT5 0 0 0 0 0 X = Don't care PREVIOUS ADDRESS SOA[1:0] = 00 If the previous two LSBs are 00, bits OD15 : OD0 reflect the fault status (Table 11). Table 11. Fault Status OD15 0 OD14 0 OD13 UVF OD12 OTW OD11 OTS OD10 NM OD9 OL5 OD8 OVL5 OD7 OL4 OD6 OVL4 OD5 OL3 OD4 OVL3 OD3 OL2 OD2 OVL2 OD1 OL1 OD0 OVL1 OD13 (UVF) = Under-voltage Flag on VBAT OD12 (OTW) = Over-temperature Prewarning Flag OD11 (OTS) = Over-temperature Flag for all outputs OD10 (NM) = Normal mode Note OD9, OD7, OD5, OD3, OD1 (OL5, OL4, OL3, OL2, OL1) = Open Load Flag at Outputs 5 through 1, respectively. OD8, OD6, OD4, OD2, OD0 (OVL5, OVL4, OVL3, OVL2, OVL1) = Overload Flag for Outputs 5 through 1, respectively.This corresponds to OCHI or OCLO faults. A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0]. OVL=OCHI1+OCHI2+OCLO PREVIOUS ADDRESS SOA[1:0] = 01 If the previous two LSBs are 01, bits OD15 :O D0 reflect reflect the temperature status (Table 12). Table 12. Overload Status OD15 0 OD14 1 OD13 UVF OD12 OTW OD11 OTS OD10 NM OD9 OC5 OD8 OTS5 OD7 OC4 OD6 OTS4 OD5 OC3 OD4 OTS3 OD3 OC2 OD2 OTS2 OD1 OC1 OD0 OTS1 OD13 (UVF) = Under-voltage Flag on Vbat OD12 (OTW) = Over-temperature Prewarning Flag OD11 (OTS) = Over-temperature Flag for all outputs OD10 (NM) = Normal mode Note OD9, OD7, OD5, OD3, OD1 (OC5, OC4, OC3, OC2, OC1) = High Over-current Shutdown Flag for Outputs 5 through 1, respectively OD8, OD6, OD4, OD2, OD0 (OTS5, OTS4, OTS3, OTS2, OTS1) = Over-temperature Flag for Outputs 5 through 1, respectively A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0]. OC=OCHI1+OCHI2 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS PREVIOUS ADDRESS SOA[1:0] = 10 If the previous two LSBs are 10, bits OD15 : OD0 reflect the status of the 10XS3535 (Table 13). Table 13. Device Status OD15 1 OD14 0 OD13 UVF OD12 OTW OD11 OTS OD10 NM OD9 0 OD8 OV OD7 OD6 OD5 OD4 RC OD3 OD2 pin OD1 OD0 fail FOG_ FLASH IGN_O ON ER_ON N FOG pin FLASHER IGN pin CLOCK OD13 (UVF) = Under-voltage Flag on Vbat OD12 (OTW) = Over-temperature Prewarning Flag OD11 (OTS) = Over-temperature Flag for all outputs OD10 (NM) = Normal mode OD8 (Overvoltage) = Over-voltage Flag on Vbat in real time OD7 = Indicates the state of internal FOG_ON signal, as described OD5 = Indicates the state of internal IGN_ON signal OD4 (RC) = Logic [0] indicates a Front Penta Device. Logic [1] indicates a Rear Penta Device OD3 (FOG pin) = indicates the FOG pin state in real time OD2 (FLASHER pin) = Indicates the FLASHER pin state in real time OD1 (IGN pin) = Indicates the IGN pin state in real time OD0 (CLOCK fail) = Logic [1], which indicates a clock failure. The content of this bit is reset by read operation. in Figures 11 OD6 = Indicates the state of internal FLASHER_ON signal PREVIOUS ADDRESS SOA[1:0] = 11 If the previous two LSBs are 11, bits OD15 : OD0 reflect the status of the 10XS3535 (Table 14). Table 14. Output Status OD15 1 OD14 1 OD13 UVF OD12 OTW OD11 OTS OD10 NM OD9 0 OD8 0 OD7 X OD6 X OD5 X OD4 OUT5 OD3 OUT4 OD2 OUT3 OD1 OUT2 OD0 OUT1 OD13 (UVF) = Under-voltage Flag on Vbat OD12 (OTW) = Over-temperature Prewarning Flag OD11 (OTS) = Over-temperature Flag for all outputs OD10 (NM) = Normal mode OD4 (OUT5) = Logic [0] indicates the OUT5 voltage is lower than VOUT_TH. Logic [1] indicates the OUT5 voltage is higher than VOUT_TH OD3 (OUT4) = Logic [0] indicates the OUT4 voltage is lower than VOUT_TH. Logic [1] indicates the OUT4 voltage is higher than VOUT_TH OD2 (OUT3) = Logic [0] indicates the OUT3 voltage is lower than VOUT_TH. Logic [1] indicates the OUT3 voltage is higher than VOUT_TH OD1 (OUT2) = Logic [0] indicates the OUT2 voltage is lower than VOUT_TH. Logic [1] indicates the OUT2 voltage is higher than VOUT_TH OD0 (OUT1) = Logic [0] indicates the OUT5 voltage is lower than VOUT_TH. Logic [1] indicates the OUT1 voltage is higher than VOUT_TH 10XS353 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES PROTECTION AND DIAGNOSIS FEATURES OUTPUT PROTECTION FEATURES The 10XS3535 provides the following protection features: *Protection against transients on VBAT supply line (per ISO 7637) *Active clamp, including protection against negative transients on output line *Over-temperature *Severe and resistive Over-current *Open Load during ON state These protections are provided for each output (OUT1:5). Over-temperature detection The 10XS3535 provides over-temperature shutdown for each output (OUT1:OUT5 ). It can occur when the output pin is in the ON or OFF state. An over-temperature fault condition results in turning OFF the corresponding output. The fault is latched and reported via SPI. To delatch the fault and be able to turn ON again the outputs, the failure condition must be removed (T< 175 C typically) and: *if the device was in Normal mode, the output corresponding register (bit D7) must be rewritten. Application of complete OCHI window (OCHI1+OCHI2 during t2) depends on toggling or not toggling the D7 bit. *if the device was in Fail mode, the corresponding output is locked until restart of the device: wake up from Sleep mode or VBATPOR1. The corresponding SPI fault report (OTS bit) is removed after a read operation. Over-current detections The 10XS3535 provides intelligent over-current shutdown (see Figure 12) in order to protect the internal power transistors and the harness in the event of overload (fuse characteristic). Output current OCHI (IOCHI1 and then IOCHI2) is only activated after toggling D7 bit in Normal Mode. During the switch-on, a severe short-circuit condition provided on the module connector is reported as an OCHI fault. In Fail Mode, the control of OCHI window is provided by the toggles: IGN_ON, Flasher_ON, and FOG_ON. The current thresholds (IOCHI1, IOCHI2 and IOCLO) and the time (t1 and t2) are fixed numbers for each driver. After t2, OCLO current threshold is set to protect in steady state. t1 and t2 times are compared to "on" state duration (tON) of the output. In case of the output is controlled in PWM mode during the inrush period, the tON corresponds to the sum of each "on" state duration in order to expand dynamically the transient overcurrent profile. OUT2 is default loaded with the Xenon profile. The use of H7 bulbs at this output requires SPI programming (Xenon bit). In case of overload (OCHI1 or OCHI2 or OCLO detection), the corresponding output is disabled immediately. The fault is latched and the status is reported via SPI. To delatch the fault, the failure condition must be removed and: For OCHI1: *if the device was in Normal Mode: the output corresponding register (bit D7) must be rewritten D7=1. Application of complete OCHI window depends on toggling or not toggling D7 bit. *if the device was in Fail Mode, the failure is locked until restart of the device: wake up from Sleep Mode or VBATPOR1. For OCHI2 and OCLO: *if the device was in Normal Mode: the output corresponding register (bit D7) must be rewritten D7=1. Application of complete OCHI window depends on toggling or not toggling D7 bit. *if the device was in Fail Mode, Autorestart is activated. The device Autorestart feature provides a fixed duty cycle and fixed period with OCHI1 window. Autorestart feature resets OCHI2 or OCLO fault after corresponding Autorestart period. The SPI fault reports are removed together after a read operation: OCHI1 OCHI2 OCLO - OC bit=(OCHI1) or (OCHI2) fault - OVL bit=(OCHI1) or (OCHI2) or (OCLO) fault Overvoltage detection and active clamp t1 t2 time The 10XS3535 provides an active gate clamp circuit in order to limit the maximum drain to source voltage. In case of overload on an output the corresponding switch (OUT[1 to 5]) is turned off which leads to high voltage at Figure 12. Double Over-current Window in Normal Mode 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES VBAT with an inductive VBAT line. The maximum VBAT voltage is limited at VBATCLAMP by active clamp circuitry through the load. In case of open load condition, the positive transient pulses (ISO 7637 pulse 2 and inductive battery line) shall be handled by the application. Figures 13 and 14 describe the faults management in Normal mode and Fail mode. Note: t1 and t2 please refer to Figure 12. (OCHI2 = 1) or (OT = 1) or (UV = 1) or (D7 = 0) (OCHI1 = 1) or (OT = 1) or (UV = 1) or (D7 = 0) D7 = 0 then 1 without fault and (NO_OCHI = 0) t1 (rewrite D7 = 1) and (tON OCHI2 tON = t2 without fault (NO_OCHI = 1) without fault (NO_OCHI = 1) without fault OCLO tON (tON>t2) and (rewrite D7 = 1) without fault D7=0 then 1 without fault and (NO_OCHI=1) (OCLO=1) or (OT=1) or (UV=1) or (D7=0) Figure 13. Faults Management in Normal Mode (for OUT[1:5] only) 10XS353 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES (external_ON = 0) (OT = 1) or (OCHI1 = 1) OFF-latched State (OT=1) (OT = 1 (external_ON = 0) (external_ON = 1) (t>tOCHI1) and (auto restart = 0) (t>tOCHI2) and (auto restart = 0) OFF out: OFF auto restart = 0 OCHI1 out: external (UV = 1 OCHI2 out: external (t>tOCHI1_AUTO) and (auto restart = 1) OCLO out: external (UV = 1) and (external_on = 1) (t>tautorestart) (UV* = 0) and (UV = 1) or (OCHI2 = 1) (OCLO = 1) or (UV = 1) (external_ON = 0) OFF Autorestart out: OFF autorestart=1 (external_ON = 0) 1.4 sec min external external_ON external: IGN, FLASHER, FOG external_ON: IGN_ON, Flasher_ON, FOG_ON Note: * See Autorestart strategy chapter. Figure 14. Faults Management in Fail Mode (for OUT[1:5] only) DIAGNOSTIC Open Load The 10XS3535 provides open load detection for each output (OUT1:OUT5 ) when the output pin is in the ON state. Open load detection levels can be chosen by SPI to detect a standard bulb, a Xenon bulb for OUT2 only, or LEDs (OLLED bit). Open load for LEDs only is detected during each regular switch-off state or periodically each t OLLED (fully-on, D[6:0] = 7F). To detect OLLED in fully on state, the output must be on at least t OLLED. When an open load has been detected, the output stays ON. To delatch the diagnosis, the condition should be removed and the SPI read operation is needed (OL bit). In case of a Power on Reset on VBAT, the fault will be reset. Current Sense The 10XS3535 diagnosis for load current (OUT1:6) is done using the current sense (CSNS) pin connected to an external resistor. The CSNS resistance value is defined in function to VCC voltage value. It is recommended to use resistor 500 < RCSNS < 5.0 k. Typical value is 1.0 k for 5.0 V application. The routing of the current sense sources is SPI programmable (MUX[2,0] bits). 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES The current recopy feature for OUT1:5 is disabled during a high over-current shutdown phase (t2) and is only enabled during low over-current shutdown thresholds. The current recopy output delivers current only during ON time of the output switch without overshoot (aperiodic settling). The current recopy is not active in Fail mode. With a calibration strategy, the output current sensing precision can be improved significantly. One calibration point at 25 C for 50% of FSR allows removing part to part contribution. So, the calibrated part precision goes down to +/-6.0% over [20% - 75%] output current FSR, over voltage range (10 V to 16 V) and temperature range (-40 to 125 C). With dedicated calibration points, the current recopy allows diagnosing lamp damage in paralleling operations, like as flasher topology. The Figure 15 summaries test results covering 99.74% of parts (device ageing not included) for Standard lamps and LEDs. available in CSNS output pin for MUX[2,0] bits set to "111", as described in Figure 16. typ min max 2 CSNS feedback (V) 2.5 1.5 1 0.5 0 -40 -20 0 20 40 60 80 100 Board tem perature (C) 120 140 160 180 Figure 16. Analog temperature precision The board temperature feedback is not active in Fail mode. With a calibration strategy, the temperature monitoring precision can be improved. So, one calibration point at 25 C allows removing part to part contribution, as presented in Figure 17. typ min max 2 CSNS feedback (V) 2.5 1.5 1 Orange = LED mode Blue = lamp mode (default mode) 0.5 Figure 15. Current sense precision with calibration strategy for OUT1/5 Board Temperature Feedback The 10XS3535 provides a voltage proportional to the temperature on the GND flag. This analog feedback is 0 -40 -20 0 20 40 60 80 100 Board tem perature (C) 120 140 160 180 Figure 17. Analog temperature precision with calibration strategy Output Status The 10XS3535 provides the state of OUT1:OUT5 outputs in real time through SPI. The OUT bit is set to logic [1] when the corresponding output voltage is closed to half of battery. This bit allows synchronizing current sense and diagnosing short-circuit between OUT and VBAT terminals. TEMPERATURE PREWARNING The 10XS3535 provides a temperature prewarning reported via the SPI (OTW bit) in Normal mode. The information is latched. To delatch, a read SPI command is needed. In case of a Power on Reset, the fault will be reset. 10XS353 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES EXTERNAL PIN STATUS The 10XS3535 provides the status of the FLASHER, FOG, and IGN pins via the SPI in real time and in Normal mode. FAILURE HANDLING STRATEGY A highly sophisticated failure handling strategy enables light functionality even in case of failures inside the component or the light module. Components are protected against: * Reverse Polarity * Loss of Supply Lines * Fatal Mistreatment of Logic I/O Pins * all latched faults are maintained under VCC in nominal conditions. In case VBAT is disconnected, OUT[1:5] outputs are OFF. OUT6 output state depends on the previous SPI configuration. The SPI configuration, reporting, and daisy-chain features are provided for RST is set to logic [1]. The SPI pull-up and pull-down current resistors are available. This fault condition can be diagnosed with UVF fault in OD13 reporting bit. The previous device configuration is maintained. No current is conducted from VCC to VBAT. LOSS OF VCC (DIGITAL LOGIC SUPPLY LINE) During loss of VCC (VCC < VCCUV ) and with wake=1, the 10XS3535 is switched automatically into Fail mode (no deglich time). The external SMART MOSFET is OFF. All SPI registers are reset and must be reprogrammed when VCC goes above VCCUV. The device will transit in OFF mode if VBAT < VBATPOR2. REVERSE POLARITY PROTECTION ON VBAT In case of a permanently reverse polarity operation, the output transistors are turned ON (Rsd) to prevent thermal overloads and no protections are available. An external diode on VCC is necessary in order to not to destroy the 10XS3535 in cases of reverse polarity. In case of negative transients on the VBAT line (per ISO 7637), the VCC line is still operating, while the VBAT line is negative. Without loads on OUT1:5 terminal, an external clamp between VBAT and GND is mandatory to avoid exceeding maximum rating. The maximum external clamp voltage shall be between the reverse battery condition and -20 V. Therefore, the device is protected against latch-up with or without load on OUT outputs. LOSS OF VCC AND VBAT If the external VBAT and VCC supplies are disconnected (or not within specification: (VCC and VBAT) < VBATPOR1), all SPI register contents are reset with default values corresponding to all SPI bits are set to logic [0] and all latched faults are also reset. LOSS OF GROUND (GND) During loss of ground, the 10XS3535 cannot operate the loads (the outputs (1:5) are switched OFF), but is not destroyed by the operating condition. Current limit resistors in the digital input lines protect the digital supply against excessive current (1kohm typical). The state of the external smart power switch controlled by FETOUT is not guaranteed, and the state of external smart MOS is defined with an external termination resistor. LOSS OF SUPPLY LINES The 10XS3535 is protected against the loss of any supply line. The detection of the supply line failure is provided inside the device itself. LOSS OF VBAT During an under-voltage of VBAT (VBATPOR1 < VBAT < VBATUV), the outputs [1-5] are switched off immediately. No current path from VBAT to VCC. The external MOSFET (OUT6) can be controlled in Normal Mode by the SPI if VCC remains and is above VCCUV. The fault is reported to the UVF bit (OD13). To delatch the fault, the under-voltage condition should be removed and: * To turn-on the output, the corresponding D7 bit must be rewritten to logic [1] in Normal mode. Application of the OCHI window depends on toggling or not toggling the D7 bit. * If the device was in Fail mode, the fault will be delatched by the Autorestart feature periodically. In case of VBAT < VBATPOR1 (Power OFF mode), the behavior depends on VCC: * all latched faults are reset if VCC < VCCUV, FATAL MISTREATMENT OF LOGIC I / O PINS The digital I / Os are protected against fatal mistreatment by signal plausibility check according to Table 15. Table 15. Logic I / O Plausibility Check Input / Output LIMP (PWM) CLOCK SPI (MOSI, SCLK, CS) Signal Check Strategy Debounce for 10ms Frequency range (bandpass filter) WD, D10 bit internal toggle In case the LIMP input is set to logic [1] for a delay longer than 10ms typical, the 10XS3535 is switched into Fail mode. In case of a (PWM) Clock failure, no PWM feature is provided and the bit D7 defines the outputs state. In case of SPI failure, the 10XS3535 is switched into Fail mode (see Figure 18) 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES WD Bit D10 0 1 timeout 75ms window watchdog 75ms window watchdog 0 D10 is toggled after the window watchdog Fail Mode activation Figure 18. Watchdog window 10XS353 36 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS TYPICAL APPLICATIONS Figure 19 below shows full vehicle light functionality, including fog lights, battery redundancy concept, light substitution mode, and Fail mode. Pa ig ht Lo B e w am Fl Be as am P a her rk in g Li gh t e ar t Sp gh Li g Fo e a m B h ig eam Br e w L o as h e H i rk Sp ar gh ng Fl Li Li g gh Fo H t CP 100nF VBAT MOSI, MISO, SCLK CP CS CLOCK 10XS3535 CornerLight Switch (Front Left) CS CLOCK 10XS3535 CornerLight Switch (Front Right) VBAT 100nF RST IGN LIMP FLASHER FOG CSNS RST IGN LIMP FLASHER FOG CSNS VCC VCC t gh t Li gh og Li t e rF r iv i g h ea R rD eL t h ea s R c en Lig Li op er h St as F l ht ig lL gh ce riv t ne St se Lig op L ig ht Fl L i g h t as h t Ta her il Li gh t ea r Fo g Li i Ta R R Li ea rD 100nF CP 100nF 35XS3500 VBAT CS CLOCK CS CLOCK CP 35XS3500 VBAT CornerLight Switch (Rear Left) VCC RST IGN LIMP FLASHER STOP CSNS RST IGN LIMP FLASHER STOP CSNS CornerLight Switch (Rear Right) VCC Microcontroller Watchdog VCC (5.0V) WD (5.0V) VBAT Ignition Stop Light Flasher VBAT Figure 19. Typical Application EMC & EMI PERFORMANCES The 10XS3535 is compliant to CISPR25 Class5 with 22nF decoupling capacitor on OUT[1:5] 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 37 PACKAGING PACKAGING DIMENSIONS PACKAGING PACKAGING DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below. PNA SUFFIX 24-PIN PQFN 98ART10511D ISSUE 0 10XS353 38 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGING DIMENSIONS PNA SUFFIX 24-PIN PQFN 98ART10511D ISSUE 0 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 39 PACKAGING PACKAGING DIMENSIONS PNA SUFFIX 24-PIN PQFN 98ART10511D ISSUE 0 10XS353 40 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGING DIMENSIONS PNA SUFFIX 24-PIN PQFN 98ART10511D ISSUE 0 10XS3535 Analog Integrated Circuit Device Data Freescale Semiconductor 41 REVISION HISTORY REVISION HISTORY Revision 1.0 2.0 3.0 Date 5/2010 7/2010 9/2010 Description of Changes * * * * * * * * * Initial Release Changed PN to MC10XS3535PNA Changed classification to Advance Information Added Minimum Output Current Reported in CSNS for OUT[2-4](14) to Table 3. Added Minimum Output Current Reported in CSNS for OUT[1,5](14) to Table 3. Added Minimum Output Current Reported in CSNS for OUT[2-4] in LED Mode(14) to Table 3. Added Minimum Output Current Reported in CSNS for OUT[1,5] in LED Mode(14) to Table 3. Added Note: Output current value computed after leakage current removal (open load condition)to Table 3. Added Under-voltage Deglitch Time parameter. 4.0 5/2011 10XS353 42 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2010-2011. All rights reserved. MC10XS3535 Rev. 4.0 5/2011 |
Price & Availability of 10XS3535
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |